1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a semiconductor memory device in which data is refreshed in response to a refresh designating signal designating data refresh.
2. Description of the Background Art
Generally, in a dynamic random access memory (hereinafter referred to as a DRAM), it is necessary to perform refreshing operation (data retaining operation) of each memory cell MC in a prescribed refresh period (of, for example, 64 ms) for holding data.
FIG. 3 is a circuit block diagram showing a structure of a DRAM having an operation mode for refreshing operation. There are several types of refreshing modes (such as RAS only refresh mode, self refresh mode). Here, CAS before RAS refresh mode (hereinafter referred to as CBR refresh mode) will be described as an example.
Referring to FIG. 3, the DRAM includes a timing circuit 31, a row .multidot. column address buffer 32, a CBR determining circuit 33, a CBR counter 34, an address selector 35, a gate circuit 36, a row address decoder 37, a sense amplifier driving circuit 38, a column decoder 39, a memory mat 40 and a data input/output buffer 50.
Timing circuit 31 outputs an activating signal .phi.R for activating row address decoder 37, an activating signal .phi.SA for activating sense amplifier driving circuit 38 and an activating signal .phi.L for activating column decoder 39, respectively, as prescribed timing, in accordance with externally applied control signals /RAS, /CAS and /WE.
Row .multidot. column address buffer 32 latches externally applied address signals A0 to An (where n is a natural number) at a time of fall of control signal /RAS, and applies the latched address signals A0 to An to address selector 35 as a row address RA. Row .multidot. column address buffer 32 latches address signals A0 to An at the time of fall of control signal /CAS, and applies the latched address signals A0 to An to column decoder 39 as a column address CA.
CBR determining circuit 33 outputs a refresh designating signal .phi.CBR in response to setting of CBR refresh mode, that is, in response to the fall of control signal /CAS before the fall of control signal /RAS.
CBR counter 34 is a counter having the same number of bits n+1 as address signals A0 to An, which counts fall of refresh designating signal .phi.CBR and outputs n+1 bits of internal address signals A0' to An' to address selector 35 as a refresh address X.sub.CBR.
Address selector 35 is controlled by refresh designating signal .phi.CBR, and it couples row .multidot. column address buffer 32 and row address decoder 37 at the time of reading and writing operations, while this couples CBR counter 34 and row address decoder 37 at the time of refreshing operation.
Gate circuit 36 interrupts input of activating signal .phi.L from timing circuit 31 to column decoder 39 in response to refresh designating signal .phi.CBR, so as to inactivate column decoder 39 at the time of refreshing operation.
Memory mat 40 includes a plurality of memory cells MC arranged in row and column directions, a word line WL provided corresponding to each row, a bit line pair BL, /BL provided for each column, and a sense amplifier 42 and a column selection gate 47 provided corresponding to each bit line pair BL, /BL. Memory cells MC, word lines WL and bit line pairs BL, /BL constitute a memory cell array 41.
Each memory cell MC includes an N channel MOS transistor Q for accessing, and a capacitor C for storing data. MOS transistor Q and capacitor C are connected in series between a cell plate and one of the paired bit lines BL, /BL, and MOS transistor Q has its gate connected to the word line WL of the corresponding row. When the word line WL is raised to the "H" level which is the activation level, MOS transistor Q is rendered conductive so that charges (data) is exchanged between capacitor C and one of the paired bit lines BL, /BL.
Sense amplifier 42 includes N channel MOS transistors 43 and 44 connected between paired bit lines BL, /BL and a node N31, respectively, and P channel MOS transistors 45 and 46 connected between paired bit lines BL, /BL and a node N32, respectively. MOS transistors 43 and 45 have their gates both connected to bit line /BL, and MOS transistors 44 and 46 have their gates both connected to bit line BL. Nodes N31 and N32 receive sense amplifier activating signals /SE and SE output from sense amplifier driving circuit 38. Sense amplifier 42 is activated by sense amplifier activating signals /SE, SE, and amplifies small potential difference generated between the paired bit lines BL, /BL by the activation of memory cells MC through the power supply voltage Vcc.
Column selection gate 47 includes N channel MOS transistors 48, 49 connected between paired bit lines BL, /BL and signal input/output lines IO, /IO, respectively. MOS transistors 48 and 49 have their gates connected to column decoder 39 through a column selection line CSL. When column selection line CSL is raised to the "H" level which is the activation level, MOS transistors 48 and 49 are rendered conductive, so that bit line pair BL, /BL and signal input/output line pair IO, /IO are connected to each other.
Row address decoder 37 is activated by activating signal .phi.R, and raises one of the plurality of word lines WL0, WL1, . . . of memory cell array 41 to the active level of "H", in accordance with a row address RA or a refresh address X.sub.CBR applied from row .multidot. column address buffer 32 or CBR counter 34 through address selector 35.
Sense amplifier driving circuit 38 is activated by activating signal .phi.SA and applies sense amplifier activating signal SE, /SE to sense amplifier 42.
Column decoder 39 is activated by activating signal .phi.L and raises one of the plurality of column selection lines CSL to the active level of "H" in accordance with column address CA applied from row .multidot. column address buffer 32.
At the time of writing, data input/output buffer 50 applies an externally applied data to selected memory cell MC in response to an externally applied control signal /WE. At the time of reading, data input/output buffer 50 outputs data of a selected memory cell MC externally in response to an externally applied control signal /OE.
FIG. 4 is timing chart showing the operation of the DRAM shown in FIG. 3.
In a normal write/read cycle, control signal /RAS falls before control signal /CAS. Therefore, an output signal .phi.CBR from CBR determining circuit 33 is kept at the "L" level, which is an inactive level. Therefore, address selector 35 outputs row address RA output from row .multidot. column address buffer 32 to row address decoder 37. Thereafter, in accordance with activating signals .phi.R, .phi.L, .phi.SA generated by timing circuit 31, row address decoder 37, sense amplifier driving circuit 38, column decoder 39 and data input/output buffer 50 are activated, and write/read operation is performed.
More specifically, at the time of writing, column decoder 39 raises column selection line CSL of a column in accordance with the column address signal CA to the active level of the "H", and renders column selection gate 47 conductive.
Data input/output buffer 50 applies write data to a selected pair of bit lines BL, /BL through signal input/output line pair IO, /IO, in response to control signal /WE. Write data is applied as potential difference between bit lines BL and /BL.
Thereafter, row address decoder 37 raises a word line WL of a row corresponding to the row address RA to the active level of "H", so that MOS transistor Q of the memory cell MC belonging to the row is rendered conductive. To the capacitor C of the selected memory cell MC, charges of which amount correspond to the potential of bit line BL or /BL are stored.
In reading operation, first, the potential of the bit lines BL and /BL are equalized at a prescribed potential Vcc/2, and thereafter, row address decoder 37 raises the word line WL of the row corresponding to the row address RA to the active level of "H". Consequently, the potentials of bit lines BL and /BL change slightly, in accordance with the amount of charges stored in the capacitor C of the activated memory cell MC.
Thereafter, sense amplifier driving circuit 38 raises sense amplifier activating signal SE to the "H" level, and lowers sense amplifier activating signal /SE to the "L" level, so as to activate sense amplifier 42. When the potential of bit line BL is slightly higher than the potential of bit line /BL, resistance values of MOS transistors 44 and 45 become smaller than the resistance values of MOS transistors 43 and 46, so that the potential of bit line BL is pulled up to the "H" level, while the potential of bit line /BL is pulled down to the "L" level. By contrast, when the potential of bit line /BL is slightly higher than the potential of bit line BL, resistance values of MOS transistors 43 and 46 become smaller than the resistance values of MOS transistors 44 and 45, so that the potential of bit line /BL is pulled up to the "H" level, while the potential of bit line BL is pulled down to the "L" level.
Thereafter, column decoder 39 raises a column selection line CSL of the column corresponding to column address CA to the active level of "H", so that column selection gate 47 is rendered conductive. Data input/output buffer 50 outputs potential difference between the selected bit line pair BL, /BL, that is, read data, externally, in response to control signal /OE.
Since the charges stored in capacitor C of the memory cell MC flow out gradually even when MOS transistor Q is non-conductive, the data is refreshed in a prescribed refresh period.
In the CBR refresh cycle, control signal /RAS falls earlier than control signal /CAS. Therefore, output signal .phi.CBR of CBR determining circuit 33 is raised to the "H" level, which is the active level. Therefore, address selector 35 outputs the refresh address X.sub.CBR outputs from CBR counter 34 to row address decoder 37.
Thereafter, row address decoder 37 and sense amplifier driving circuit 38 are activated by activating signals .phi.R and .phi.SA generated by timing circuit 31, and the memory cell MC connected to the word line WL of the row corresponding to the refresh address X.sub.CBR is performed. Refreshing operation is similar to reading operation, except that column decoder 39 and data input/output buffer 50 are not activated.
By the fall of refresh designing signal .phi.CBR, CBR counter 34 is counted up, and CBR counter 34 outputs an address X.sub.CBR +1 of the row to be refreshed in the next CBR refresh operation.
The CBR refresh operation is carried out in a prescribed refreshing period, which is predetermined for the DRAM chip. The refreshing period is set considering the memory cell MC having the poorest data retention characteristic, so as to ensure data retention of every memory cell MC.
However, most of the memory cells MC in the DRAM have sufficiently higher data retention characteristic than the memory cell MC having the poorest data retention characteristic, which is used as a reference to set the refreshing period. In other words, unnecessary refreshing operation is performed on the memory cells MC having sufficiently higher data retention characteristic, which means that excessive power is consumed.
In view of the foregoing, a method has been proposed in which a refresh period setting circuit is provided for each row, so as to allow setting of refreshing period of each row to take into account a memory cell having the poorest data retention characteristic in the row, to elongate the refreshing period as a whole and to reduce excessive power consumption (see Japanese Patent Laying-Open No. 4-34794).
However, according to this method, it becomes necessary to provide a refresh period setting circuit for each row. Therefore, the number of circuits is increased and the layout area is increased. This is more true in a DRAM of a so called shared sense amplifier structure in which memory cell arrays are divided into a plurality of blocks and refreshing operation is performed block by block to reduce power consumption. Further, if the number of memory cells having poorer data retention characteristic is small as compared with the total number of memory cells, most of the refresh period setting circuits are not used and wasted.